TMS320LF2406APZAR

Product Summary

The TMS320LF2406APZAR is a digital signal processor (DSP) controller. While code-compatible with the existing C24x DSP controller device, the TMS320LF2406APZAR offers increased processing performance (40 MIPS) and a higher level of peripheral integration. The device offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flash devices of up to 32K words offer a cost-effective reprogrammable solution for volume production. The TMS320LF2406APZAR offers a password-based “code security” feature which is useful in preventing unauthorized duplication of proprietary code stored in on-chip Flash/ROM.

Parametrics

TMS320LF2406APZAR absolute maximum ratings: (1)Supply voltage range, VDD, PLLVCCA, VDDO, and VCCA: -0.3 V to 4.6 V; (2)VCCP range: -0.3 V to 5.5 V; (3)Input voltage range, VIN: -0.3 V to 4.6 V; (4)Output voltage range, VO LF240xA: -0.3 V to 4.6 V; (5)Input clamp current, IIK (VIN < 0 or VIN > VCC): ±20 mA; (6)Output clamp current, IOK (VO < 0 or VO > VCC): ±20 mA; (7)Operating free-air temperature ranges, TA: A version: -40℃ to 85℃; S version: -40℃ to 125℃; (8)Junction temperature range, TJ: -40℃ to 150℃; (9)Storage temperature range, Tstg: -65℃ to 150℃.

Features

TMS320LF2406APZAR features: (1)High-Performance Static CMOS Technology, 25-ns Instruction Cycle Time (40 MHz); 40-MIPS Performance; Low-Power 3.3-V Design; (2)Flash (LF) and ROM (LC) Device Options; (3)On-Chip Memory; (4)Boot ROM (LF240xA Devices), SCI/SPI Bootloader; (5)Up to Two Event-Manager (EV) Modules; (6)Watchdog (WD) Timer Module; (7)10-Bit Analog-to-Digital Converter (ADC); (8)Controller Area Network (CAN) 2.0B Module; (9)Serial Communications Interface (SCI); (10)16-Bit Serial Peripheral Interface (SPI); (11)Phase-Locked-Loop (PLL)-Based Clock Generation; (12)Up to 40 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins; (13)Up to Five External Interrupts (Power Drive Protection, Reset, Two Maskable Interrupts); (14)Power Management: Three Power-Down Modes; Ability to Power Down Each Peripheral Independently; (15)Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1(JTAG).

Diagrams